Release notes

Releases of documentation and code are using the same version numbers.

Note

The version numbering system (tries and) follows the semantic versioning principles; given a version number MAJOR.MINOR.PATCH, increment the:

  1. MAJOR version when you make incompatible API changes

  2. MINOR version when you add functionality in a backward compatible manner

  3. PATCH version when you make backward compatible bug fixes

1.7.0 - 2026-08-28

1.6.0 - 2026-07-26

  • TCP protocol

    • New: All returned message now include "sim_time" and "sim_time_unit" fields. This provides a timestamp on the simulation timescale.

    • New: Added command get(variables) which returns all publicly available variables (only for the Verilator integration version)

    • New: Added command get(clocks) which returns all registered clocks (only for the Verilator integration version)

  • Python client

    • Bug fix: capture output for elaboration command in setup_sim_run() function

  • Verilator integration

    • Modified: The clock registration function vsl::VslInteg::register_clock() also directly registers the corresponding variable so that it can be publicly accessed by protocol commands.

    • Bug fix: Corrected serious bug within the clock evaluation algorithm which could end up in an infinite loop when using multiple clocks.

  • New features or changes for CLI wizard configuration script:

    • New: verilog_inc_dirs configuration parameter in YAML file

    • New: verilog_arg_files configuration parameter in YAML file

    • New: name variable parameter in YAML file

    • New: build_dir configuration parameter in YAML file or as CLI option.

    • New: --makefile-top CLI option

    • New: --log-level CLI option

    • New: enable optional clock variable parameter in YAML configuration file

    • New: optional exec_version, exec_doc and bug_address configuration parameter in YAML file

    • New: user_sim_info configuration parameter in YAML file

    • Modified: In the configuration file, the choices for the variables type is limited to either int or real. Detailed type is inferred by the script from the value of width. It is also now optional, the default being int.

    • Modified: For the clock variables definition, the fields duty_cycle is now optional and defaults to 0.5.

    • New: sub_files optional entry in YAML file

1.5.0 - 2026-02-07

1.4.0 - 2025-08-22

1.3.0 - 2025-04-19

  • Added an API to support integrating Verisocks with Verilator, including full documentation

  • Included a CLI wizard script to Python package in order to facilitate the creation of top-level C++ code to use Verisocks with Verilated code

  • Modified the command get(sim_info) to return time_unit and time_precision information

1.2.0 - 2024-03-16

1.1.0 - 2024-02-07

  • Added verisocks.utils Python utilitary functions, including documentation.

  • Added Verisocks.info() method as a shortcut to implement the TCP protocol info command.

  • Corrected SPI master example for standalone execution.

  • Added a minimalistic Hello world example, working both for standalone execution or with pytest.

1.0.0 - 2024-01-04

  • First released, working version