Verilator integration

This section describes how to use Verisocks with Verilator to produce a compact and efficient model for your hardware that can be interfaced using the Verisocks commands.

With the current version (1.3) of the provided API, the following assumptions are made:

  • the verilog sources contain all the necessary stimuli to generate all required clocks and other timed events for the simulation to proceed

  • the verilation is performed using the --timing option of verilator